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FFT Chip Comparisons

Processor	Year	CMOS Tech (ľm)	Datapath Width (bits)	Dataword Format (fixed pt., block float, float pt.)	Supply Voltage (V)	Execution Time (ľsec /1024-pt xform)	Power (mW)	Clock (MHz)	Number of Chips M=DataMem C=CoeffMem	Area, 0.5ľ eff (mm^2)	I/O pads (pins)	Energy Efficiency (FFTs per Energy) See below	Processor
DASP/PAC Honeywell [1]	1988	1.2ľm	16	block float	-	102ľsec	2000 + 2000 + 5*250	-	1+1+4M+C	-	269/180/-	1.7	DASP/PAC Honeywell
PDSP16510A Mitel (Plessey)	1989?	1.4ľm	16	block float	5.0	98ľsec	3000	40	1	22	84	3.6	PDSP16510A Plessey
PDSP16515A Mitel (Plessey)	-	-	18	block float	5.0	98ľsec	-	40	1	-	84	-	PDSP16515A Plessey
L64280 LSI [5]	1990	1.5ľm	20	float	5.0	26ľsec	20,000	40	10+10	233	-	2.9	L64280 LSI
Dassault Electronique [6]	1990	1.0ľm	12	block float	5.0	6.4ľsec	24,000?	40	6	255	299	3.4	Dassault Electronique
Y. Zhu, Univ. of Calgary [7]	1993	1.2ľm	16	block float	5.0	155ľsec	-	33	1+1+2M+C	15+	132	-	Y. Zhu Univ. of Calgary
TM-66 Texas Mem Sys	-	0.8ľm	32	float	5.0	65ľsec	7000+	50	1+1+M+	-	299/?	<3.4	TM-66 Texas Mem Sys
BDSP9124/9320 Butterfly DSP	-	0.8ľm	24	block float	-	54ľsec	-	60	1+1+2M+C+	-	262/68	-	BDSP9124/9320 Butterfly DSP
Cobra, Colorado State [10]	1994	0.75ľm	23	-	5.0	9.5ľsec	7700	40	16+	1104+	391	<12.4	Cobra Colorado State
CNET E. Bidet [11]	1994	0.5ľm	10	-	3.3	51ľsec	300	20	1	100	-	13.6	CNET E. Bidet
Spiffee 1 Stanford	1995	0.7ľm, L_poly= 0.6ľm	20	fixed	3.3	30ľsec	845	173	1	25	70	27.6	Spiffee 1 Stanford
Spiffee 1 Stanford		0.7ľm, L_poly= 0.6ľm			1.1 **	330ľsec	9.5	16				223	Spiffee 1 Stanford
Spiffee Low V_t * Stanford		0.8ľm, L_poly= 0.26ľm			0.4	93ľsec	<9.7	57				>887	Spiffee Low V_t Stanford
Spiffee ULP * Stanford		0.5ľm			0.4	61ľsec	8	85				1025	Spiffee ULP Stanford
DaSP/PaC/RaS Array Microsystems	1996?	-	16	block float	5.0	131ľsec	1750 + 2000 + 3*2000	40	1+1+3	-	144/144/144	-	DaSP/PaC/RaS Array Microsystems
SNC960A Sicom	1996	0.6ľm	16	-	5.0	20ľsec	2000- 3000	65	1	-	-	9.0	SNC960A Sicom
DSP-24, DSP Architectures[13]	1997	0.5ľm	24	block float	3.3	21ľsec	3500	100	1	217	308	8.7	DSP-24 DSP Architectures
M. Wosnitza, ETH, Zurich[14]	1998	0.5ľm	32	block float	3.3	80ľsec	6000	66	1	167	180	2.4	M. Wosnitza ETH, Zurich
Radix RDA108	-	-	<=19	-	3.3	12.2ľsec	-	84	2	-	313	-	Radix RDA108
DoubleBW	2000	0.35ľm	24	float	3.3	10ľsec	8000	128	1	429	530	5.6	DoubleBW
Programmable DSP Processors
C40 Texas Instruments	-	0.7ľm	-	float	5.0	1298ľsec	4500	60	-	-	-	-	C40 Texas Instruments
SHARC ADSP-21061 Analog Devices	-	-	-	float	5.0	460ľsec	4500	40	-	-	-	-	SHARC Analog Devices
DSP32C Lucent	-	-	32	float	-	2110ľsec	-	80	-	-	-	-	DSP32C Lucent
DSP16000 Lucent	-	-	-	-	2.7	-	-	100	-	-	-	-	DSP16000 Lucent
NM6403, Module	1998	0.5ľm	32	fixed	3.3	439ľsec	1300	50	1	-	256	1.7	NM6403 Module
HiPAR-DSP 4, Universitat Hannover	1999	0.5ľm	16	fixed	-	222ľsec	5000	66	1	180	-	0.34	HiPAR-DSP 4 Universitat Hannover
Synthesizable Processors
Inventra Mentor	1997	-	20	-	-	90ľsec	-	-	-	27K gates	-	-	Inventra Mentor
Inventra Mentor	1997	-	20	-	-	90ľsec	-	-	-	27K gates	-	-	Inventra Mentor
Other Processors
Cray 2 (1-cpu)	-	-	-	float	-	1000ľsec	-	244	-	-	-	-	Cray 2 (1-cpu)
Cray Y-MP (1-cpu)	-	-	-	float	-	600ľsec	-	159	-	-	-	-	Cray Y-MP (1-cpu)
Processor	Year	CMOS Tech (ľm)	Datapath Width (bits)	Dataword Format (fixed pt., block float, float pt.)	Supply Voltage (V)	Execution Time (1024-pt ľsec/xform)	Power (mW)	Clock (MHz)	Number of Chips M=DataMem C=CoeffMem	Area, 0.5ľ eff (mm^2)	I/O pads (pins)	Energy Efficiency (FFTs per Energy) See below	Processor

FFTs per Energy = Tech * ( ²/₃ (DPath/20) + ¹/₃ (DPath/20)² ) / Power / Exec Time / 10^-6: The function shown above, FFTs per Energy, gives an adjusted number of 1024-point complex FFTs that can be calculated for a fixed amount of energy, and attempts to factor out Technology and the datapath word width, DPath. It makes use of the observation that about ¹/₃ of the energy consumption of the 20-bit Spiffee processor scales as DPath² (e.g., multipliers) and about ²/₃ of the circuits scale in complexity linearly with DPath. The constant 10^-6 is added to put the result into a more convenient range.
* Low V_t Spiffee processors: The Spiffee Low V_t version has not yet been fabricated, although portions of it have been. Numbers shown are from extrapolated measurements, and will be better than shown because the power number includes additional circuits that the baseline Spiffee1 chip does not. The Spiffee ULP numbers are from simulations.
** For this case, an nwell bias was set to -0.5v. The current drawn was approximately 10ľA.

[1] S. Magar, et. al., ICASSP88. Assume memory power = 250mW per chip.
[5] P. Ruetz, et. al., ICPR90.
[6] Private communication with designer.
[7] Private communication with designer.
[10] G. Sunada, et. al., ICCD '94.
[11] E. Bidet, C. Joanblanq, and P. Senn, CICC '94
[13] Simulated results. Private communication with designer.
[14] M. Wosnitza, "A High Precision 1024-point FFT Processor for 2D Convolution", ISSCC '98.

A few more FFT processors

16 point DFT chip - Macquarie University
FFT/Convolution processor - TNO-FEL
Ediz Cetin's 256-point FFT chip
1997, 0.7um, 24-bit fixed-point I/O paths, 39-bit internal datapaths, 5.0 V supply, 40MHz clock, 2.7mm x 3.2mm, 256-point complex FFT in 102.4ľs
Austek A41102 single chip 256-point complex FFT processor. Calculates 2 to 256 point DFT's on up to 24-bit input data (in each I and Q) with 24-bit complex outputs. 256-point FFTs calculated in 102.4 usec.
16-point, 24-bit, 0.6um, 60MHz, 16.88mm^2 FFT chip by G. C. Cardarilli, M. Iannuccelli, and A. Salsano
Send me a link you know of!

FFT board-level products

Catalina Research (LH-9124,...)
Valley Technologies (DSP-24, TI C6201, LH-9124, DSP32C processors)
Bores (LH9124, DSP32C, 56K processors)

Programmable DSP processors

Soft FFT cores

IComm Tech Inc.

Misc. FFT stuff

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