Index: raminit.c
===================================================================
--- raminit.c	(revision 2744)
+++ raminit.c	(working copy)
@@ -324,7 +324,9 @@
 	 *	   001 = 2 Mem clocks after CAS# (Registered Dimms)
 	 * [31:23] Reserved
 	 */
-	PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0),
+
+//	PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0), //ORIG
+	PCI_ADDR(0, 0x18, 2, 0x8c), 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(1 << 0), //change!
 	/* DRAM Config Low Register
 	 * F2:0x90
 	 * [ 0: 0] DLL Disable
@@ -395,12 +397,19 @@
 	 *	   111 = Oldest entry in DCQ can be bypassed 7 times
 	 * [31:28] Reserved
 	 */
-	PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000, 
+//	PCI_ADDR(0, 0x18, 2, 0x90), 0xf0000000,  //orig
+	PCI_ADDR(0, 0x18, 2, 0x90), 0xc0000000, 
+	(1 << 29)| //change
+	(1 << 28)| //change
+
 	(4 << 25)|(0 << 24)| 
 	(0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| 
 	(1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| 
 	(2 << 14)|(0 << 13)|(0 << 12)| 
-	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| 
+
+//	(0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)|  //orig
+
+	(0 << 11)|(0 << 10)|(1 << 9)|(0 << 8)|  //CHANGE DUAL DIMM ENABLE
 	(0 << 3) |(0 << 1) |(0 << 0),
 	/* DRAM Config High Register
 	 * F2:0x94
@@ -1201,7 +1210,7 @@
 	if (unbuffered && registered) {
 		die("Mixed buffered and registered dimms not supported");
 	}
-#if 1
+#if 0
 	// yhlu debug: Athlon64 939 can do dual channel, but it uses unbuffered DIMMs
 	if (unbuffered && is_opteron(ctrl)) {
 		die("Unbuffered Dimms not supported on Opteron");
@@ -1397,9 +1406,9 @@
 		die("min_cycle_time to low");
 	}
 	print_spew(param->name);
-#ifdef DRAM_MIN_CYCLE_TIME
+//#ifdef DRAM_MIN_CYCLE_TIME
 	print_debug(param->name);
-#endif
+//#endif
 	return param;
 }
 
@@ -1425,6 +1434,10 @@
 
 
 	value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	print_debug("NB CAP REG:");
+	print_debug_hex32(value);
+	print_debug("\n");
+
 	min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
 	bios_cycle_time = min_cycle_times[
 		read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
@@ -1946,6 +1959,11 @@
 			}
 		}
 	}
+
+
+//HGDUHDDHJDHKJDKJHDKHDKHDKJ
+	clocks = 4;
+
 	if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
 		die("Unknown Trwt\r\n");
 	}
@@ -1983,6 +2001,10 @@
 	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
 	dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
 	rdpreamble = 0;
+	print_err("DIVISOR: \n");
+	print_err_hex16(divisor);
+	print_err("\n");
+
 	if (is_registered(ctrl)) {
 		if (divisor == ((10 << 1)+0)) {
 			/* 100Mhz, 9ns */
@@ -2046,11 +2068,15 @@
 				/* 5ns */
 				rdpreamble = ((5 << 1)+0);
 			} else {
-				/* 7ns */
-				rdpreamble = ((7 << 1)+0);
+				/* 5.5ns */
+				rdpreamble = ((5 << 1)+1);
 			}
 		}
 	}
+	print_err("RDPREAMBLE: \n");
+	print_err_hex16(rdpreamble);
+	print_err("\n");
+
 	if ((rdpreamble < DCH_RDPREAMBLE_MIN) || (rdpreamble > DCH_RDPREAMBLE_MAX)) {
 		die("Unknown rdpreamble");
 	}
@@ -2089,7 +2115,7 @@
 		}
 		else {
 			/* 6ns */
-			async_lat = 6;
+			async_lat = 7; //change!
 		}
 	}
 	dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
Index: northbridge.c
===================================================================
--- northbridge.c	(revision 2744)
+++ northbridge.c	(working copy)
@@ -556,7 +556,7 @@
 	base  |= (resource->base >> 8) & 0xffffff00;
 	base  |= 3;
 	limit &= 0x00000048;
-	limit |= ((resource->base + resource->size) >> 8) & 0xffffff00;
+	limit |= ((resource->base + resource->size - 1) >> 8) & 0xffffff00;
 	limit |= (resource->index & 3) << 4;
 	limit |= (nodeid & 7);
 	f1_write_config32(reg + 0x4, limit);
Index: incoherent_ht.c
===================================================================
--- incoherent_ht.c	(revision 2744)
+++ incoherent_ht.c	(working copy)
@@ -830,6 +830,8 @@
 static inline unsigned get_nodes(void);
 #endif
 
+unsigned get_sbdn(unsigned);
+
 #if RAMINIT_SYSINFO == 1
 static void ht_setup_chains_x(struct sys_info *sysinfo)
 #else
@@ -909,6 +911,7 @@
 			next_busn+=0x3f+1;
 
 #if K8_ALLOCATE_IO_RANGE == 1			
+
 			/* io range allocation */
 		        tempreg = nodeid | (linkn<<4) |  ((next_io_base+0x3)<<12); //limit
 		        pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);